DC decoding logic circuit - has input pairs of series MOSFETs coupled in parallel via complementary MOSFET switches

摘要

The DC coding logic circuit has its response speed increased by reducing the number of MOSFETs in series. The input signals (X) are applied to the gates of several MOSFETs connected in series pairs. (The pairs are in parallel via MOSFET switches controlled by switching pulses). One switch signal (32) is applied to the gate of a p-channel MOSFET (P10 etc.) in series with the n-channel logic pair (N10, N11, etc.) between a supply pole and a common rail. The unswitched end of each MOSFET series pair is connected to the common rail, which receives a complementary switching signal. This switching signal also controls an n-channel output switch (N14).