| 摘要 |
The setting circuit comprises first and second switches; a first signal generating circuit which generates a pulse signal each time the first switch is closed; a second signal generating circuit for generating 0 and 1 level output signals from a first output terminal when the second switch is opened and closed and a pulse signal from a second output terminal each time the second switch is opened; a ring counter circuit including cascade connected first to third shift registers each connected to receive the pulse signal from the second signal generating circuit at the reset terminal thereof, said ring counter operating as a 3 digit ring counter when the second switch is opened but as a four digit ring counter when the second switch is closed, thereby producing control signals for setting the display mode and the correction mode of the electronic timepiece from the first output terminal of the signal generating circuit and predetermined output terminals of the ring counter circuit. |
