| 摘要 |
A random access memory device of the MOS integrated circuit type using an array of one-transistor storage cells employs bistable sense amplifier circuits, one located in the center of each column line. The bistable circuits have current-limiting control devices in series therewith and the control devices are selected by the address circuits in a manner such that during an initial sensing period the current is low, then during a later period more current may be permitted for a higher level output. In parts of the array which are not being accessed by the current address, the increased current level is not permitted, thus reducing power dissipation.
|
