| 摘要 |
<p>1484458 Control of A.C. motors; inverting SCRAGG POWER DRIVES Ltd 6 Dec 1974 [19 Dec 1973] 58740/73 Headings H2F and H2J A digital speed control system for an induction motor comprises means for producing a pulsed input signal proportional in frequency to desired motor speed; speed setting means, connected to the output of the pulse signal producing means, and including means for dividing the number of pulses therefrom by a constant factor and a ring counter, connected to be driven by the dividing means, for generating a series of pulse train waveforms for selectively switching an inverter to produce an induction motor power supply ; and voltage control means, connected to the output of the pulse signal producing means, and including a monostable multivibrator for generating a fixed duration output pulse for each input pulse from the pulse signal producing means, and mixing gates, modulated in response to the fixed duration pulses, connected to one-half only of the outputs of the ring counter such that the inverter output voltage is controlled to be directlv proportional to the frequency of the pulsed input signal and hence to the frequency of the power supply. In Fig. 1 a three phase squirrelcage induction motor 6 is supplied from an inverter 5 comprising a six-transistor bridge circuit with parallel protection diodes. Fig. 2 (not shown) and the control system comprises an oscillator 1 supplying divider 2 and monostable multivibrator 8, which controls mixing gates 7 connected to three of the six pulse train waveforms produced by a three-stage ring counter and waveform generator 3, these waveforms each having a pulse width and spacing of 180 degrees and the pulses of each waveform being phase-displaced by 60 degrees with respect to those of the preceding waveform. A theoretical analysis of the control system operation, valid for the three-phase inverter 5 or a single-phase one supplying a single-phase induction motor, is derived from the duration t of the pulse from multivibrator 8, the period T of the pulses from oscillator 1, the factor n of divider 2 and the maximum output voltage Vm of the inverter 5 at full modulation. Typical switching operations of the inverter transistors are described, Fig. 3 (not shown). Fig. 4 shows details of members 2, 3, 7 and 8, wherein a clock pulse for the divider 2 is formed by a differentiating circuit R1, C1 and a gate G1, member 3 consists of an integrated circuit interconnected with gates G2, G3, and the gates G4, G5, G6 of the member 7 are controlled by a pulse from multivibrator 8 of width determined by the product of resistor R2 and capacitor C2 connected as shown to the integrated circuit constituting this multivibrator.</p> |
