发明名称 |
Non-volatile random access memory system |
摘要 |
A non-volatile random access memory system includes a memory array circuit having a plurality of unit non-volatile memory cells arranged in a matrix array. Each unit memory cell includes a flip-flop circuit and two MNOS transistors into which a data in the flip-flop is written and from which the data written therein is transferred to the flip-flop. The system also includes means for selecting a desired one of the unit memory cells and an input-output circuit adapted to supply a data to the selected unit cell and deliver the data read out of the selected unit cell. The system further includes a source voltage variation detector circuit adapted to deliver, when the source voltage for the memory array circuit is rendered ON, a control signal including a readout signal for reading the data in the MNOS transistors into the flip-flop or a source voltage variation detector circuit adapted to generate a control signal including a write signal for writing a data in the flip-flop circuit into the MNOS transistors when the source voltage is rendered OFF and a readout signal for reading the data in the MNOS transistors into the flip-flop circuit when the source voltage is rendered ON, and means for interrupting in synchronism with the control signal a data transfer path between the selected unit memory cell and the input-output circuit so as to prevent any influence from an external circuit when a data transfer is effected between the flip-flop circuit and the MNOS transistors.
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申请公布号 |
US4044343(A) |
申请公布日期 |
1977.08.23 |
申请号 |
US19760681557 |
申请日期 |
1976.04.29 |
申请人 |
TOKYO SHIBAURA ELECTRIC CO., LTD. |
发明人 |
UCHIDA, YUKIMASA |
分类号 |
G11C14/00;(IPC1-7):G11C11/40 |
主分类号 |
G11C14/00 |
代理机构 |
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主权项 |
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地址 |
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