| 摘要 |
1,238,688. Integrated circuits. TEXAS INSTRUMENTS Inc. 3 Dec., 1968 [29 Jan., 1968], No. 57360/68. Heading H1K. An integrated circuit comprises electronic components formed of polycrystalline semiconductor material overlying an insulating layer covering a body of semi-conductor material containing further components. The polycrystalline material is fine grained and is produced by deposition at a temperature of less than 900‹ C. at a rate of less than 1 Á/min. The polycrystalline material may form a resistor or the plates of a capacitor, or may be utilized to form an FET or a unijunction transistor. In a first embodiment, Fig. 1 (not shown) and Fig. 2, a transistor 12 is formed in a monocrystalline body 11 which is covered with an insulating layer 14. Part of the emitter region 22 is exposed by photo-masking and etching and a layer of polycrystalline semi-conductor material is deposited. This layer is masked and etched to leave a strip 20 extending over the surface from the emitter region to form a resistor. Ohmic contacts 26, 28 of gold or aluminium are applied to the base and collector regions of the transistor and a lead 30 is bonded directly to the end of the polycrystalline resistor remote from the emitter region. A first interconnection plane comprising molybdenum, tantalum or tungsten layers may be formed over the first insulating layer and covered with a second insulating layer on which the polycrystalline layer is deposited. Metal conductors can be used to interconnect the monocrystalline and polycrystalline components. The polycrystalline material may be doped during deposition by the inclusion of a suitable compound of the impurity. In a second embodiment, Fig. 3 (not shown), a capacitor is formed by covering an extended area (40) of polycrystalline material with an insulating layer (44) and a metal layer (42), the polycrystalline material forming one plate of the capacitor and its resistivity determining in part the capacitance of the device. In a modification, Fig. 4 (not shown), a capacitor comprises interleaved polycrystalline layers (40, 50, 48, 52), alternate ones of which are connected together, separated by layers of insulating material. In an alternative modification, Fig. 5 (not shown) the extended polycrystalline area (40) is provided with a diffused region (60) of opposite conductivity type over the majority of its surface and is covered with an insulating layer (44) and a metal layer (62) which is connected to part of the polycrystalline layer of the original conductivity type. The diffused layer (60), which in effect forms a capacitor plate interleaved between two other plates, is contacted by a conductive track (61). In a third embodiment, Fig. 6 (not shown), the monocrystalline substrate (11) contains two transistors and the polycyrstalline layer (40) extends over the insulating layer (14) between them and has portions (68, 70) extending through apertures (69, 71) in the insulating layer into contact with the base region of one transistor and the emitter region of the other transistor. A diffused region (78) of opposite conductivity type is formed in the polycrystalline layer at a position between the points of contact (68, 70) with the transistors and forms the gate of an FET or the emitter of a unijunction transistor. The substrate and polycrystalline material may be, Si, Ge or a III-V compound such as GaAs, the insulating layer may be of silicon nitride or silicon oxide produced by RF sputtering or by decomposing silane in the presence of ammonia or oxygen respectively, and the polycrystalline layer may be deposited by the decomposition of silane or of other tetrahalides such as GeCl 4 and SiCl 4 , and may be doped with Ga, P, B, As or Sb. Diffused P-type regions may be produced by decomposition of BBr 3 to form a boron glaze which is heated to drive in the boron. |
