Processor controlled data manipulator - retains data if power fails and enables data content of memory units to be refreshed

摘要

A processor controlled arrangement for the manipulation of data contained on one or more data stores of small data systems (1,a,b,c,d) is designed to provide data retention in the event of power supply failure whilst maintaining the ability to vary the data content. Each data register is a semiconductor repetitively reprogrammable ROM which can be selectively connected to the data and address highway of the processor-controlled arrangement. An additional store may be connected as variation register. It is connected on one side to a programming unit which is connected to an operator's unit for data input, and on the other side operates an erasing device (2).