| 摘要 |
1481373 Error correction INTERNATIONAL BUSINESS MACHINES CORP 21 May 1975 [18 Aug 1974] 21871/75 Heading G4A In a random access memory system including error correction means, each stored data word includes a plurality of check bits used to correct a single bit error in the word and indicate the presence of multiple error, such multiple error in two (or more) words being corrected with the aid of two (or more) additional stored words, each byte of each of the two additional words having been formed by bit-wise modulo-2 addition of the corresponding bytes of the data words (after, in the case of the second additional word, multiplying each of the bytes by a respective power of the companion matrix of a primitive binary polynomial of the code). Syndrome bits are derived from each data word (including its check bits) to indicate error/noerror and decoded by ANDs to indicate singleerror/multiple-error (in conjunction with the error/no-error indication) and locate single error (if present) for correction. Two "accummulators" also receive the words to derive syndromes from which multiple errors in up to two (or more) words are corrected using the output of the previous circuitry to indicate which words have multiple errors. The memory holds a plurality of blocks of words, each block being 16 data words (with check bits) and the 2 (or more) additional words relating to them, the blocks being stored on multi-array wafers such that each block is spread over 4 wafers, 4 data words per wafer with each half data word being in a different array, and the additional words being in different arrays from the data words. |
