HIGH FREQUENCY CHARACTER RECEIVER

摘要

A receiver is disclosed for synchronized character pulse processing in a time slot interchange system. The receiver analyzes the phase of a character start pulse for synchronizing succeeding pulses of the character with out-of-phase clock signals of the same frequency. A delay line is included in the receiver for generating a plurality of partially coincident output signals on plural phase delay line ports and in response to received character pulses on an input data channel. A plurality of receiver subcircuits monitor each of the delay line output ports and each comprises a plurality of storage elements which are operated by clock signals and outputs at the monitored ports for maintaining a prescribed number of most recent port state samples. Logic circuitry is responsive to prescribed states of the storage elements for detecting the arrival of a start pulse and for selecting for synchronization a preferred one of the subcircuits from which approximate midpoint samples of the start pulse and succeeding character pulses are obtained for processing through a shift register to utilization circuitry.