Circuit arrangement for a quartz controlled electrical clock

摘要

A circuit arrangement for a quartz controlled electrical clock comprising an oscillator stage a frequency divider separated from the oscillator stage by a gate controlled by a control logic unit, an output stage connected to the frequency divider and a stepping motor connected to the output stage, the control logic unit responding to a command signal to open the gate and disconnect the oscillator stage from the frequency divider with the frequency divider retaining its memory content at the instant of disconnection and with no current flowing through the drive coils of the stepping motor.