发明名称 Biasing arrangement for push-pull amplifier
摘要 A biasing arrangement comprising: a first transistor for driving a pair of field effect transistors (FET's) jointly forming a push-pull amplifier; a second transistor connected in series in the collector circuit of the first transistor, the voltage across the second transistor being applied as the gate-bias voltage for the FET's; and a constant current source connected to the base of the second transistor for causing a substantially constant current to flow through a resistor connected between the collector and base of the second transistor. With this arrangement, across the resistor is developed a stabilized sufficiently large voltage as compared with the base to emitter voltage of the second transistor. Thus, the gate bias voltages of the FET's are stabilized against the fluctuations of the ambient temperature.
申请公布号 US4037166(A) 申请公布日期 1977.07.19
申请号 US19760667438 申请日期 1976.03.16
申请人 NIPPON GAKKI SEIZO KABUSHIKI KAISHA 发明人 YOKOYAMA, KENJI
分类号 H03F3/18;H03F3/30;(IPC1-7):H03F3/18 主分类号 H03F3/18
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