PROCESS FOR FABRICATING INSULATED GATE FIELD EFFECT TRANSISTOR STRUCTURE

摘要

An improved and simplified process for fabricating a complementary insulated gate field effect transistor structure having complementary p-channel and n-channel devices in the same semiconductor substrate wherein the source/drain regions of at least one of the complementary p-channel or n-channel field effect devices are formed by the steps of introducing an impurity of one conductivity type and then introducing an impurity of the opposite conductivity type, one of the impurities having a relatively greater concentration than the other so that the one impurity counterdopes the other and the source/drain regions are characterized by the conductivity type of the one impurity.