发明名称 |
Digital phase locked loop for navigation systems - is designed specially for microwave systems such as TACAN and includes a/d converter and sequence register |
摘要 |
<p>The phase-locked loop generates clock pulses synchronised with the passage through zero of an input data signal, e.G. for use in navigation systems. An A/D convertor continuously converts the input signal into a digital signal which is checked and stored by a memory when it receives a clock pulse. When a given digital signal count is reached an instruction sequence register reads out the count in synchronism with the zero passage of the input signal and generates a carry pulse at the end of the count. The carry pulse is fed to a pulse generator to produce a synchronous output clock pulse which leads or lags the zero passage of the input signal by the counting time of the instruction sequence register. A circuit feeds the output clock pulse to the memory which ensures this pulse and a second output clock pulse are synchronized with the zero passage of the input signal.</p> |
申请公布号 |
FR2335098(A1) |
申请公布日期 |
1977.07.08 |
申请号 |
FR19750037609 |
申请日期 |
1975.12.09 |
申请人 |
GENERAL DYNAMICS CORP |
发明人 |
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分类号 |
G01S1/44;H03L7/00;(IPC1-7):03K5/153;01S1/04 |
主分类号 |
G01S1/44 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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