| 摘要 |
A semiconductor read/write memory comprised of an array of cells, each having a single active element that is a IGFET device formed in a recess with one source or drain region located directly above and its other source or drain region located within a buried storage capacitor. The gate of each device is connected to an address line in the array, and transverse diffused bit lines interconnect the drains of the devices in aligned and spaced apart cells. Voltage applied via an address line activates a gate to charge its buried capacitor and store a signal when its connected bit line is also activated. Readout of stored charges is controlled by the address line through the connected bit line in the conventional manner. A memory device with an array of such single element cells can be fabricated by forming an array of N-type buried layer diffusions in a P substrate, depositing an epitaxial layer of lightly doped P material that extends above the buried layer diffusions, forming a relatively thin diffusion of N material spaced directly above the buried layer, forming a recess that passes through the thin N layer and the epitaxial layer into the thicker buried N layer, and thereafter forming a gate within the recess. |
