| 摘要 |
A signal converter circuit for converting a binary signal delivered from a bipolar transistor logic circuit into another binary signal adapted for application to a MIS transistor logic circuit. The converter circuit comprises first, second and third stages; the first stage includes a source follower circuit, the second stage includes a series connection of a pair of parallel-connected MIS FETs and a switching MIS FET, and the third stage includes an inverter circuit. The output of the third stage is fed back to the gate of one of the pair of MIS FETs in the second stage so that the converter output has binary levels acceptable to a MIS logic circuit.
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