| 摘要 |
A propagation line adder may be fabricated by replicating a unit circuit along a sense and reference propagation path. Each unit circuit corresponds to bits of the same order of magnitude of the binary addends. Selected segments of the sense propagation path are set a specified logical potential value and are coupled according to control signals generated within the unit circuit in response to the addend bits. The reference propagation path is then discharged and a sense amplifier, coupled to each segment of the reference and sense propagation paths, detects the state on corresponding segment of the sense propagation path. The propagation line adder implements an algorithm which produces the binary sum of two numbers by complementing the exclusive-or function of the addends according to a shifted product function. The shifted product function includes a carry in bit as its lowest order bit.
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