发明名称 AUXILIARY SIGNAL SUPERIMPOSING SYSTEM
摘要 PURPOSE:To limit a pulse width distortion of a decoded auxiliary signal within one bit of a main signal by converting information representing a change in the auxiliary signal into violation occurrence interval and sending the result. CONSTITUTION:A main signal input (a) inputted to a transmission section 1 is converted into a CMI code string by a CMI code conversion circuit 3. On the other hand, the leading of an auxiliary signal input (b) inputted to the transmission section 1 is detected by a leading detection circuit 4 and the trailing is detected by a trailing detection circuit 5. All n-bit, violation designation circuit 6 designates violation of n-bit interval with an auxiliary signal leading detection signal (e) of the circuit 4 and an m-bit violation designation circuit 7 designates the violation of m-bit of interval by using all auxiliary signal trailing detection signal (d) from the circuit 5 to form a violation designation pulse (e). The pulse (e) is inputted to the circuit 3 and violation is applied to the CMI code string of the main signal for the time slot of the pulse (e). Thus, a signal (f) subjected to violation corresponding to the change point of the input (b) is sent to the reception section 2.
申请公布号 JPH0362641(A) 申请公布日期 1991.03.18
申请号 JP19890196679 申请日期 1989.07.31
申请人 NEC CORP;NEC ENG LTD 发明人 KIKUCHI TOSHIAKI;NISHIMURA KEIJIRO
分类号 H04J13/00 主分类号 H04J13/00
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