发明名称 |
Memory patching circuit with counter |
摘要 |
A read only memory (ROM) patching arrangement is disclosed for providing valid output information whenever ROM word locations containing invalid information are addressed. The disclosed arrangement uses a plurality of small capacity PROMs as a decoder to detect the receipt of each address word representing a defective ROM locaton. Upon each detection of a defective address, the decoder temporarily inhibits the output of the ROM and causes a small auxiliary memory to output valid program information as a substitute for that in the defective ROM location. A counter is used as a supplemental addressing source for both the decoder and the auxiliary memory. This increases the patching capability by subdividing the decoder and the auxiliary memory into 2n segments where n is the number of bits supplied by the counter.
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申请公布号 |
US4028683(A) |
申请公布日期 |
1977.06.07 |
申请号 |
US19750622939 |
申请日期 |
1975.10.16 |
申请人 |
BELL TELEPHONE LABORATORIES, INCORPORATED |
发明人 |
DIVINE, CHARLES HAMMAN;O'NEILL, JOHN FRANCIS |
分类号 |
G11C17/00;G06F9/06;G06F9/22;G06F9/26;G06F9/445;G06F11/28;G11C29/04;(IPC1-7):G06F13/00 |
主分类号 |
G11C17/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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