| 摘要 |
PURPOSE:To suppress a time loss to obtain the result of calculation within a short time by outputting a delay signal whose delay time is shorter than a delay signal whose delay time is longest by a prescribed time among delay output signals in a delay means as a delay signal of a next stage integrated circuit. CONSTITUTION:Delay means D0-DM-1 generating a delay signal respectively with a prescribed delay time with respect to an input signal or a delay signal from a pre-stage are provided to apply a prescribed calculation processing to each delay signal. Then a delay signal whose delay time is shorter than a delay signal whose delay time is longest by a prescribed time among delay output signals in the delay means D0-DM-1 is outputted as a delay signal to a next-stage integrated circuit (signal processing LSI 22). Thus, even when there is a timewise loss till the delay signal outputted from the integrated circuits 21, 22 is inputted to an arithmetic processing part in the integrated circuits 22, 23 of the next stage, the time loss is reduced substantially by a prescribed time. |
