Pulse frequency multiplier for controlling supply circuit - has clock signals counted between input pulses and held in buffer memory

摘要

The pulse frequency multiplier, for coding angular signals and controlling a motor supply circuit, has a time base generator (5,6) producing two constant-frequency clock signals clocking two separate counters (4,9) in a chain. The two counters are separated by a buffer memory (7) and the outputs of the second counter (a backwards counter) are connected to an output gate (10). The gate's own output is passed back to reset the second counter. The first counter counts the number of input pulses between two successive clock pulses, whilst the second counter counts backwards the number in the buffer in synchronisation with its clocking pulses.