Decoder structure for a folded logic array

摘要

This specification describes a decoder for use in a programmable logic array (PLA) of the type having opposite ends of input lines of the array connected to outputs of different decoders. Instead of using the outputs of two two-bit decoders to drive four input lines, as was previously done, four one-bit decoders are used to drive the four input lines. This arrangement permits the one-bit decoders with minor modifications to be used to perform four one-bit decodes of four input signals, two two-bit decodes on two sets of two input signals on either side of the array and one two-bit decode on two input signals that are on opposite sides of the array.