发明名称 General purpose sequence controller
摘要 A general purpose sequence controller wherein a schematic electric circuit diagram comprising a ladder network of circuit lines disposed between two vertical bus lines is changeable and simulated by a special purpose control program. A logic operation circuit comprises first and second circuit means for examining an external input signal in accordance with examine commands of logical AND and OR functions, respectively, first and second memory means for temporarily memorizing the examined results of the first and second circuit means, respectively, third memory means for temporarily memorizing the application of the examine command of the logical OR function, and identifying circuit means for identifying the examined results of the logic operations in accordance with the contents of the first, second and third memory means.
申请公布号 US4025902(A) 申请公布日期 1977.05.24
申请号 US19740479039 申请日期 1974.06.13
申请人 TOYODA KOKI KABUSHIKI KAISHA 发明人 NAKAO, HISAJI;NARUSE, KATUTOSHI;HASEGAWA, KAZUHIKO;KAWADE, SADAO;TOKURA, YASUFUMI;MATSUNO, KAZUO
分类号 G05B19/05;(IPC1-7):G06F3/00;G06F9/06;G06F15/46 主分类号 G05B19/05
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