| 摘要 |
A circuit for generating a logic function and its logical complement of N binary variables utilizing MOS transistors which are all of the same conductivity type. The circuit may include an N input NAND gate comprising N MOS transistors and a load element, the conduction paths of the transistors connected in series with the load element to form a first series circuit and an inverter circuit having N+1 MOS transistors, the conduction paths of which are connected in series to form a second series circuit. Each series circuit is connected between the same operating voltage terminals and the two are interconnected to one another in such manner that the power dissipation of the circuit compares favorably with a CMOS inverter. |
