发明名称 SERIAL DATA PROTECTION DETECTION CIRCUIT
摘要 <p>PURPOSE:To simplify circuit constitution by using a NAND gate in the case of the forward protection and using an OR gate in the case of the backward protection for an output of each stage shifted by each shift register in response to the number of stages of the forward protection and the backward protection for the protection detection. CONSTITUTION:An n-bit data 13 subjected to multiplex processing is shifted by n-bit with shift registers 21, 22, 23, 24 connected serially one after another and in the case of the detection by the forward 5-stage protection to an optional bit, a current data 13 and outputs of the shift registers 21-24, in total five outputs are noticed and when all outputs are logical 1, an output 0 of NAND gate 25 is detected. Similarly, in the case of the detection by the backward 5-stage protection, when the current data 13 and all of the respective outputs of the shift registers 21-24 are logical 0, an output 0 of an OR gate 26 is detected, and the output of an AND gate 27 is the result of protection detection.</p>
申请公布号 JPH0373631(A) 申请公布日期 1991.03.28
申请号 JP19890207969 申请日期 1989.08.14
申请人 NEC CORP 发明人 FUKUSHIGE MINORU
分类号 H04J3/06;H04L7/08 主分类号 H04J3/06
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