| 摘要 |
A system is provided for coupling an indeterminate number of peripheral devices to a central processing unit (CPU) through a single receptacle. A cable connected to an interface unit (IU) of a first device plugs into the CPU receptacle. Cables of subsequent IUs are plugged into receptacles connected to earlier plugged IUs, thus connecting the cables of all devices in series and the device IU's themselves in parallel. One type of IU is for a magnetic tape cassette and includes a timeout circuit to determine when certain types of programming errors have occurred. A binary digit is set in a status register for that and other types of errors. The status register is read under program control of the CPU, thus providing for the flexibility of haulting operation or bypassing the program section having an error for unattended operation of the CPU.
|
