Multiphase series-parallel-series charge-coupled device registers with simplified input clocking

摘要

The invention comprises a charge-coupled device shift register for storing and transferring bits of information in the form of small packets of charge. The apparatus utilizes multiphase clocking to allow for high density storage within the register which is comprised of three sections: serial input section, central storage section and serial output section. The serial input section receives charge packets synchronously from an injector circuit and is driven by two phase clocking. The central section forms the heart of the storage and transfer mechanism and is driven by multiphase clocking. The serial output section, also driven by two-phase clocking, synchronously emits charge packets which are sensed and amplified by a sense amplifier circuit.