NEGATIVE RESISTANCE SEMICONDUCTOR DEVICE

摘要

1473394 Negative resistance circuits MATSUSHITA ELECTRONICS CORP 16 Aug 1974 [20 Aug 1973 30 Aug 1973] 36199/74 Heading H3T [Also in Division H1] At least one of the interconnections between a pair of complementary depletion mode FET's cross-coupled as shown in Fig. 1 is provided by the at least partial overlap of two highly doped semi-conductor regions. Fig. 3 shows two junction gate FET's; an N channel device comprising N+ type source and drain regions 10, 11, an N type channel region 7 and a P type gate region 8; and a P channel device comprising P+ type source and drain regions 13, 14, a P type channel region 9 and an N+ type gate region 12. The source regions 11 and 14 overlap and are sufficiently highly doped to provide ohmic contact therebetween. Fig. 4 shows a similar combination, but in which the N channel device has an N type surface inversion channel region 21 either induced by the presence of a SiO 2 layer 20, or ion implanted. P type region 17, contacted via P+ type surface region 22, forms a "back-gate" arrangement. Both these embodiments utilize N type epitaxial layers 7 on P type substrates 6. Fig. 5c also shows the combination of a surface inversion channel FET with a back gate 25/26 and a junction gate FET. In this case a common N+ type region 28 serves both as the gate region of the J-FET (with drain and source regions 26, 27) and as the drain region of the surface inversion channel FET (with source and channel regions 29, 21). The regions 27, 29 may be interconnected by virtue of their high doping and a mutual overlap, as shown, or by means of a metallization layer.