发明名称 EPITAXIALLY GROWN SILICON LAYERS WITH RELATIVELY LONG MINORITY CARRIER LIFETIMES
摘要 <p>1455840 Semi-conductor devices WESTINGHOUSE ELECTRIC CORP 28 Dec 1973 [5 Jan 1973] 59942/73 Heading H1K In a semi-conductor device, a Si layer having an impurity concentration less than 10<SP>17</SP> atoms/ cm.<SP>3</SP> and a minority carrier lifetime greater than 50 nanosecs. is epitaxially deposited on a Si layer doped with P or B to a surface concentration greater than 10<SP>19</SP> atoms/cm.<SP>3</SP>, preferably greater than 10<SP>20</SP> atoms/cm.<SP>3</SP> In Fig 1 MOS capacitors are formed on a substrate 10 of spinel or preferably sapphire. A layer 12 of Si is deposited on substrate 10 by pyrolysis of SiH 4 , and is then doped with P derived from PH 3 to a concentration of 10<SP>20</SP>-10<SP>21</SP> atoms/ cm.<SP>3</SP> A second Si layer 13 is similarly formed, being lightly doped with P 1 or As derived from AsH 3 , and is then conventionally masked and etched to form islands, over which a layer 14 of SiO 2 is deposited. Windows 16 are formed in layer 14, and metal, e.g. evaporated Al, is deposited to form electrodes 18 and contacts 17, the latter being subsequently alloyed to the underlying Si layer 12. In the bipolar NPN mega transistor shown in Fig. 10, the substrate is formed by a monocrystalline Si body 20 having an impurity concentration of P of 10<SP>20</SP> atoms/cm.<SP>3</SP> Si layers 22, doped with As to 8 Î 10<SP>14</SP> atoms/cm.<SP>3</SP>, and 24, doped with B to 10<SP>16</SP> atoms/cm.<SP>3</SP>, are epitaxially deposited on body 20, followed by conventional etching, oxide-coating, emitter diffusion, and metallization steps. In modifications, the transistor is formed on a sapphire substrate (33, Fig. 11, not shown) and the emitter region (27<SP>11</SP>, Fig. 12, not shown) is formed by epitaxial deposition. Fig. 15 (not shown) depicts a complementary MOS transistor arrangement formed on a sapphire substrate, and in Fig. 16 (not shown) a similar construction replaces a P<SP>+</SP>N<SP>-</SP>P<SP>+</SP> transistor with a P<SP>+</SP>P<SP>-</SP>P<SP>+</SP> transistor for operation in a deep-depletion enhancement mode. In Fig. 17, an image-sensing target of a TV camera comprises a sapphire substrate 70, an epitaxial layer 72 of heavily doped Si, and a further, lightly doped, epitaxial layer 73. Donor impurities are dffused through windows in an oxide layer 75 to form P-type regions 77, and so produce a mosaic of diodes which, in operation, face the incident radiation 78.</p>
申请公布号 CA1010158(A) 申请公布日期 1977.05.10
申请号 CA19730188305 申请日期 1973.12.17
申请人 WESTINGHOUSE ELECTRIC CORPORATION 发明人 RAI-CHOUDHURY, PROSENJIT;SCHRODER, DIETER K.
分类号 H01J9/233;C30B25/02;C30B29/06;H01J9/20;H01J29/45;H01L21/205;H01L21/329;H01L21/331;H01L21/86;H01L27/12;H01L29/73;H01L29/78;H01L29/786;H01L29/94;H01L31/10 主分类号 H01J9/233
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