Phase-locked loop frequency synthesizer

摘要

A phase-locked loop frequency synthesizer is described not having the uncontrolled modulation of its output normally associated with such a synthesizer due to a detection dead band inherent in the phase/frequency comparator which is a principal part thereof. The frequency synthesizer includes, as is conventional, a reference oscillator and an oscillator for generating the synthesizer output. The comparator is also included as is conventional to detect unwanted deviations of the phase and frequency of the synthesizer output so they can be corrected. In order to compensate for the inability of the comparator to detect small unwanted deviations, a pulse generator is added to the synthesizer to apply what is, in effect, an intentional periodic phase error signal greater than the dead band difference. This causes the phase of the desired output to be corrected in a controlled manner which will prevent undesired frequency modulation of its output.