LOW POWER CLOCK DRIVER

摘要

A low power dissipation circuit for generating clock pulses comprises a plurality of solid state devices which are normally off and draw only leakage current in their quiescent state. The clock pulse is started by a signal to a set side driver and is stopped by a signal to a reset side driver. The input drivers remain on only during the time they are being driven. The output drivers for generating the clock pulse comprises a pair of switching transistors which remain on only while the clock switching pulses are being generated.