| 摘要 |
<p>The error correction circuit for a computer installation utilises a comparison system for two strings of data-bits (aj, bj, 5=0, 1, .....J-1) for tin operands (A, B). The data strngs pass through a gate control section and split into sections passing through XOR, OR and AND gates. Each group of data on passing through the second set of gates is attached to a parity bit to form an FCC (ERROR corrected code) group. A second parity bit is generated for each corrected string to transmit the corrected data to the next stage of the system. The sequence of checks is carried out in conformity with a decision table.</p> |
