| 发明名称 |
BUCKET MULTIPLICATION EQUIPMENT |
| 摘要 |
PURPOSE:The number of processing wait circuit is reduced to 2 kinds, and waiting for signals of plural units are made possible. In this way, hardware is minimized and error such as overrun, under run, etc. can be reduced, increasing the number of storage terminal unit. |
| 申请公布号 |
JPS5252306(A) |
申请公布日期 |
1977.04.27 |
| 申请号 |
JP19750127493 |
申请日期 |
1975.10.24 |
| 申请人 |
HITACHI SEISAKUSHO KK;NIPPON DENSHIN DENWA KOSHA |
发明人 |
HEITOU KOUSHI;NISHIJIMA TOMIHISA;TOKI RIYUUICHI;SASAOKA MAKOTO |
| 分类号 |
H04J3/00;H04L5/22;H04L5/24;H04L29/00 |
主分类号 |
H04J3/00 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
|
| 地址 |
|
