Integrated arithmetic unit for computing summed indexed products

摘要

The invention relates to an integrated arithmetic unit for computing summed indexed products and suitable for fabrication by large scale integration techniques. The arithmetic unit comprises a vector adder and a vector multiplier. The vector adder includes a pair of serially connected summers each with one sign controlled input. The vector multiplier comprises two single precision multiplication logics whose outputs are each provided with a sign control. The appropriately signed outputs of the two multiplication logics are then summed to provide the output of the arithmetic unit. The input data are introduced and the processed output data, both of which may be complex, are derived from the unit in bit serial, word parallel computation when a greater speed of computation is required and used repetitively with suitable multiplexing provisions when a lesser speed of computation is required. A major application of the arithmetic units is in the computation of multiple point Fast Fourier Transforms (FFT). In the FFT application, the arithmetic units are normally operated in parallel with serial input and serial output memories for each paralleled sets of units.