发明名称 |
Interpolation-decimation circuit for increasing or decreasing digital sampling frequency |
摘要 |
A general purpose interpolator-decimator circuit for increasing or decreasing the sampling rate of a digital signal by a factor L/M, where L and M are integers, is disclosed. The circuit includes means for determining each output sample by multiplying a sequence of previous input samples by a set of coefficients and accumulating the resulting products. L sets of coefficients, in which each coefficient is a function of the factors L and M, are stored in a specific sequence which permits sequential addressing of both the coefficients and input signal samples. A multistage decimator cascaded with a multistage interpolator to effect a narrow-band FIR filter is also disclosed.
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申请公布号 |
US4020332(A) |
申请公布日期 |
1977.04.26 |
申请号 |
US19750616283 |
申请日期 |
1975.09.24 |
申请人 |
BELL TELEPHONE LABORATORIES, INCORPORATED |
发明人 |
CROCHIERE, RONALD ELDON;RABINER, LAWRENCE RICHARD |
分类号 |
H03M7/32;G10L19/00;H03H17/00;H03H17/06;H03M7/00;H04B14/04 |
主分类号 |
H03M7/32 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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