| 发明名称 |
TIMING OUTPUT GENERATION CIRCUIT |
| 摘要 |
<p>PURPOSE:To prevent the generation of the lack of the timing output by arranging the start signal abstraction circuit in addition to the first and the second delay signals, and by using the total 4 signals, dividing the output of the abstraction circuit into two signals.</p> |
| 申请公布号 |
JPS5250659(A) |
申请公布日期 |
1977.04.22 |
| 申请号 |
JP19750127069 |
申请日期 |
1975.10.22 |
| 申请人 |
FUJITSU LTD |
发明人 |
MIZOGUCHI YUTAKA;TAKAMURA MORIYUKI;TSUTOME MEGUMU |
| 分类号 |
H03K5/1252;G06F1/04;G06F1/06;H03K5/00;H03K5/13 |
主分类号 |
H03K5/1252 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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