| 发明名称 |
TIMING OUTPUT GENERATION CIRCUIT |
| 摘要 |
<p>PURPOSE:Not only to enlarge the allowance range which makes the timing output generate, but also to increase the variation margin of the input start signal by synthesizing several supplementary start signals having the delay time and the pulse width which are fixed in advance.</p> |
| 申请公布号 |
JPS5250657(A) |
申请公布日期 |
1977.04.22 |
| 申请号 |
JP19750127067 |
申请日期 |
1975.10.22 |
| 申请人 |
FUJITSU LTD |
发明人 |
MIZOGUCHI YUTAKA;TAKAMURA MORIYUKI;TSUTOME MEGUMU |
| 分类号 |
G06F1/04;H03K5/00;H03K5/04;H03K5/13 |
主分类号 |
G06F1/04 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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