首页
产品
黄页
商标
征信
会员服务
注册
登录
全部
|
企业名
|
法人/股东/高管
|
品牌/产品
|
地址
|
经营范围
发明名称
LATERAL PIT EXCAVATING METHOD BY MEANS OF METHOD OF SHIELD CONSTRUCTION
摘要
申请公布号
JPS5249634(A)
申请公布日期
1977.04.20
申请号
JP19750125144
申请日期
1975.10.17
申请人
TAIHOU KENSETSU KK
发明人
KASHIMA YUTAKA
分类号
E21D9/06;E21D9/12;E21D9/13
主分类号
E21D9/06
代理机构
代理人
主权项
地址
您可能感兴趣的专利
LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE COMPRISING THE SAME AND LIGHTING SYSTEM
LIGHT RECEIVING DEVICE AND IMAGE SENSOR
POWER SEMICONDUCTOR DEVICES HAVING SUPERJUNCTION STRUCTURES WITH IMPLANTED SIDEWALLS AND METHODS OF FABRICATING SUCH DEVICES
LIQUID CRYSTAL DISPLAY
METHOD FOR FABRICATING TRANSISTOR WITH THINNED CHANNEL
FINFET AND METHOD FOR FORMING THE SAME
SEMICONDUCTOR DEVICE WITH AN SGT AND METHOD FOR MANUFACTURING THE SAME
Semiconductor Device Structure and Method of Forming Same
Semiconductor Device having Group III-V Material Active Region and Graded Gate Dielectric
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
LOW END PARASITIC CAPACITANCE FINFET
PERFORMANCE OPTIMIZED GATE STRUCTURES
SEMICONDUCTOR DEVICES INCLUDING CAPACITORS AND METHODS FOR MANUFACTURING THE SAME
ORGANIC MAGNETOELECTROLUMINESCENCE FOR TRANSDUCTION BETWEEN MAGNETIC AND OPTICAL INFORMATION
ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE
OPTICAL GLASS
SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF, AND STATIC RANDOM ACCESS MEMORY CELL
Low Leakage Non-Planar Access Transistor for Embedded Dynamic Random Access Memory (eDRAM)
FIN FIELD EFFECT TRANSISTORS AND FABRICATION METHOD THEREOF
Contoured Package-on-Package Joint
