Circuit arrangement for storing an electrical analog signal

摘要

There is shown two frequency dividers with the same division ratio connected through first and second logic gate members to a clock generator. The phase difference between the outputs of the frequency dividing networks is proportional to the analog signal to be stored. Alternative circuit means are described for connecting the phase difference to a reference signal for comparing with a "new" analog signal. The comparison provides one of two logic conditions, depending on the relative magnitude of the signal represented by the phase difference at the output of the dividing networks and the "new " analog signal to be stored. These logic conditions operate one of respective ones of said first and second logic gate members to alter the flow of pulses into the respective dividing network, whereby the phase difference between the output of the dividing networks is now proportional to the "new" analog signal. During the "store" mode the circuit is provided with additional circuit means for incrementally changing the value of the analog signal.