发明名称 Synchronous mode data transmission multiplier interface - has bistable units corresponding to number of connected terminals with units having inputs coupled in opposition on data lines
摘要 <p>The multiplier interface has permanent analysing means of the rest and active states of the data lines which actuates automatically the blocking of the other lines as soon as one of them passes to the active state. The lines are unblocked as soon as the line passes back into the rest state. The multiplier has n bistable units (JHK), n being the number of terminals which can be connected. The bistable units are respectively associated with the n terminals and have their inputs J and K coupled in opposition to the data lines. The system has a logic circuit with a first group of inputs coupled to the output of the n bistable units. A record group of inputs are connected to the data lines which supply, when a line becomes active, a timing signal which initiates the operation of the bistable unit associated with the line and the blocking of the other units.</p>
申请公布号 FR2325122(A2) 申请公布日期 1977.04.15
申请号 FR19750028574 申请日期 1975.09.18
申请人 SERVICES INFORMATIQUE CIE INTERN 发明人 JEAN GLOTIN ET LUC VERDIER
分类号 H04L5/00;(IPC1-7):08C15/00;06F13/00;04J3/00 主分类号 H04L5/00
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