| 摘要 |
The methods result in starting material on substrates in which dielectrically isolated integrated circuits, each including a plurality of active devices having substantial gains at high frequencies and small geometries, can be manufactured. One method utilizes a silicon wafer having a [100] crystallographic orientation, on which a P+ layer is formed. This P+ layer has an exposed high concentration surface and a relatively low concentration surface interfacing the wafer. A first insulating material is then formed on the high concentration surface and a first supporting material is formed on the insulating material. The P+ layer provides an etch retardant for an anisotropic etch which removes much of the wafer to expose a substantially planar P+ surface of relatively low concentration on which a thin layer of high quality monocrystalline silicon is epitaxially formed. If a P+ buried layer is not desired, then the process is continued by providing a second insulating layer on the epitaxial silicon with a second supporting material thereon. Next, the first supporting material, first insulating layer and the P+ layer are removed to provide starting material which does not have a P+ buried layer therein. |
