| 发明名称 |
CONTROL SYSTEM OF DIFFERENT SPEED MEMORY REFRESH |
| 摘要 |
PURPOSE:The memory corresponding refresh busy display circuit is reset by answering signal of plural memories of different speed. Then reset memory is given by memory access in order to use the memory effectively. |
| 申请公布号 |
JPS5247335(A) |
申请公布日期 |
1977.04.15 |
| 申请号 |
JP19750123381 |
申请日期 |
1975.10.13 |
| 申请人 |
NIPPON DENKI KK;NIPPON DENSHIN DENWA KOSHA;OKI DENKI KOGYO KK;HITACHI SEISAKUSHO KK;FUJITSU KK |
发明人 |
MAKINO HIDEYO;MASUO KAZUYUKI;MASUNAKA YOSHIHISA;HIYAMA KUNIO;URUSHIHARA TETSUO |
| 分类号 |
G06F12/00;G06F12/06;G11C11/406 |
主分类号 |
G06F12/00 |
| 代理机构 |
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代理人 |
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