FIELD EFFECT TRANSISTOR PROTECTION CIRCUIT AND ITS USE IN CLOCK PHASE GENERATORS

摘要

A field effect transistor (FET) protection circuit adapted to operate at high switching speeds and to avoid hot electron operation of voltage stressed FET bootstrap drivers. The circuit comprises a voltage control means adapted to maintain a combined gate and drain to source voltage of FET devices within a characteristic hot electron operational voltage range, by connecting a plurality of FET devices (3, 5) in series, by connecting the common nodes of successive series connected devices (3, 5) to a specified voltage source, by clamping the gate voltage, by providing timing pulses that define particular combinations of gate and drain to source device voltages, or by providing width to length ratios adapted to provide close voltage tracking between input drain voltages and output source voltages. The operation of the hot electron voltage control means is particularly described with respect to embodiments using voltage stressed bootstrap driver FETs to generate on chip clock phases.