Storage matrix with single transistor memory elements - has FET with U-shaped drain electrode and connections to storage capacitor and bit line

摘要

The single transistor memory element has a drain (30) source (20) and gate (40) electrodes. The bit line conductor (10) is connected to gate electrode, and the source (20) is a doped region mounted on a silicon substrate of p-type conductivity. The drain electrode has a U-shaped profile and its dimensions are such that in normal operation no electrical connection can be made with the doped source region. Meander-shaped connections are used to form a matrix array out of the single unit elements. An insulating film is provided between gate electrode (40) of the FET and the gate electrode (50) of a storage capacitor. A number of parallel word-lines are provided, each alterante line have a connection to the FET associated with one bit line and the intermediate word-lines associated with the others.