发明名称 ADDRESS DECODER FOR USE WITH MULTICHANNEL ANALYZERS
摘要 <p>1432235 Comparator DRESSER INDUSTRIES Inc 28 March 1973 [14 April 1972] 14988/73 Heading G4M [Also in Division G1] A comparator contains two sets of adders 70, 71, 72 and 73, 74, 75 each set coupled to form a nine bit adder and each receiving the same nine bit number A 0 -A 8 . One adder receives a binary output from a set of thumb wheel switches 80 and the other adder receives a binary signal from a second set of switches 81. The switches set respectively upper and lower limits to the number A 0 -A 8 and their inverted value is fed to the adders. A "1" output at pin 14 of adder 75 indicates that number A 0 -A 8 is greater than that from switches 81. A "0" output at pin 14 of adder 72 indicates that A 0 -A 8 is less than or equal to the the number from switches 80. AND gate 90 receives the output from adder 75 and the inverted output from adder 72 to indicate whether number A 0 -A 8 is between the preset limits or equal to the upper limit.</p>
申请公布号 CA1007764(A) 申请公布日期 1977.03.29
申请号 CA19730165173 申请日期 1973.03.05
申请人 DRESSER INDUSTRIES, INC. 发明人 CULVER, RICHARD B.
分类号 G01V5/06 主分类号 G01V5/06
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