| 摘要 |
1468218 Data recording ELECTRICITE DE FRANCE (SERVICE NATIONAL) 29 May 1974 [29 May 1973] 23846/74 Heading H3H To save on memory capacity required for recording data, digital samples representing a time-varying input f are passed through shift register stages 5 0 -5 15 and the middle sample in a group of three consecutive stages is eliminated if its value does not differ by more than a set amount from the arithmetic mean of the outer two samples, the time between the retained samples being recorded in a corresponding shift register stage 9 1 -9 15 . As shown, a time-varying analogue input f is converted at 1 into digital samples 4 which are stepped progressively through shift register stages 5 0 -5 15 . Prior logic 66 selects the three consecutive stages which hold the oldest samples separated by equal time intervals for connection via multiplexers 23a, 23b, 23c to the analyser 39. When a sample is eliminated, only the more recent samples are advanced and I unit is added to the appropriate time register stage 9 1 -9 15 . Only those samples reaching the end stage 5 15 are memorized in store 18 together with associated time interval data from 9 15 . Details of the logic and analyser are given, Figs. 4 to 6 (not shown). |
