| 摘要 |
<p>PURPOSE:To simplify a circuit by operating a memory device with suitable switching refresh operation and data transferring operation between a memory cell array and a register in a prescribed refresh cycle. CONSTITUTION:In the cycle that an inverting column address strobe CAS signal goes to be a low level in a time limit, with which a first inverting low address strobe RAS signal falls, after the falling edge of an inverting VSYNC signal is detected, an arbitrating circuit 112 generates a control signal for data transferring to a timing generator 111. Here, each time the control signal for data transferring is received, a data transferring counter 102 alternatively outputs control signals TGL and TGU to open respective data transferring gates which are divided into two. Then, the data transferring between a memory cell array part 106 and a register 109, which is provided corresponding to a bit line, is executed with being divided into two in a word line direction.</p> |
