| 摘要 |
<p>PURPOSE:To decrease the data read time from a memory cell by decreasing the amplitude of a column line potential corresponding to the potential amplitude of a column line, that is, 0, 1 of storage data in a memory cell to reduce the time required for charge/discharge of the column lines. CONSTITUTION:When a transistor (TR) 11 whose drain is connected to a corre sponding column line 12 is selected in response to an output of row and column decoders 14, 15, the column line 12 is discharged and an output potential 03 of an inverter 23 having the lowest threshold voltage is stable when the potential is equal to the sum of the potential of the column line 12 and a threshold volt age of a TR 19 and an inverter 21 outputs logical 1. When a TR 11 whose drain is not connected to the corresponding column line 12 is selected, the col umn line 12 is charged toward a power supply potential +V via a load MOS TR 19 and the inverter 21 outputs 0 when the output potential 02 of an inverter 22 having the highest threshold voltage is equal to the sum of the threshold voltage of a TR 18 and a potential of the column line 12. Thus, the charge/ discharge time of the column line 12 attended with the data read is reduced.</p> |
