发明名称 ADDER
摘要 PURPOSE:To reduce the area occupied by an operational amplifier on a chip and the power consumption by using switched capacitor circuits. CONSTITUTION:An adder is constituted to include first and second input terminals IN1 and IN2 to which signals to be added are applied, an operational amplifier A1, switched capacitor circuits C2, S1, S2, and C4, S3, S4 which are connected between the input part of the operational amplifier A1 and input terminals IN1 and IN2, and switches capacitor circuits C6, S5, S6 which are connected between the output part and the input part of the operational amplifier A1 to form a feedback circuit. Since no resistance elements are used at all and switched capacitor circuits are used in this manner, the adder is realized with a small chip area and a low power consumption.
申请公布号 JPH01258188(A) 申请公布日期 1989.10.16
申请号 JP19880086524 申请日期 1988.04.08
申请人 NEC CORP 发明人 OKAMOTO TOSHIYUKI
分类号 G06G7/14;H03F3/34;H03F3/343;H03F3/347 主分类号 G06G7/14
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