发明名称 SIMULATION SYSTEM FOR LOGICAL CIRCUIT
摘要 PURPOSE:To monitor an oscillation state at the time of simulating a logical circuit by providing the title system with a means for monitoring a logical value on a feedback signal line. CONSTITUTION:Although some logical circuit fixes its output value (output value of level 5), oscillation may be generated in its inside (level 2-4). Since oscillation is generally generated by possitive feedback, the oscillation can be surely detected by allowing a logical value propagation monitoring means 21 to monitor the logical values of feedback signal lines 31, 32 in a feedback group.
申请公布号 JPH01292471(A) 申请公布日期 1989.11.24
申请号 JP19880122482 申请日期 1988.05.19
申请人 NEC CORP 发明人 TAKASAKI SHIGERU
分类号 H03K19/00;G06F17/50;G06F19/00 主分类号 H03K19/00
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