| 摘要 |
<p>PURPOSE:To make it unnecessary to store a data reading instruction on an internal data bus by buffering and amplifying data on the internal data bus and outputting the amplified data to an external data bus connected to external peripheral circuits. CONSTITUTION:In case of reading out data from the external peripheral devices 21-23, a CPU 10 outputs an address signal to a decoder 15 and outputs a read signal RD with an H level to the 2nd input terminal of a NAND gate NAND. In response to the signal, the decoder 15 outputs chip select signals CS4-CS6 and also outputs an external I/O signal EXIO with an H level to the 1st input terminal of the NAND. At that time, the output terminal of the NAND is turned to an L level, a 3-state buffer amplifier BA1 is disabled, a BA2 is enabled and data from the devices 21-23 are inputted through an external data bus 30, the 3-state buffer amplifier BA2 and the internal data bus 20.</p> |
